FIG. 31 is a block diagram showing configuration of an error correcting/decoding apparatus for correcting errors in concatenated code based on the conventional technology. In this figure, designated at the reference numeral 1 is a demodulator for generating a soft-decision estimate for a received bit from amplitude and phase of received waveform, at 2B a Viterbi decoder for correcting errors by selecting the highest priority path according to the soft-decision estimate output from the demodulator 1, and at 3 a CRC means for executing a cyclic redundancy check (described as "CRC" hereinafter) on an input bit sequence.
Next description is made for operation. At first, demodulation is executed in the demodulator 1, and at the same time soft-decision estimate for a received signal is computed from amplitude and a phase of the received signal. In the Viterbi decoder 2B, a path with a large path metric is selected according to the soft-decision estimate generated in the demodulator, and decoded data after trace back is generated. Then CRC is executed on an input bit sequence in the CRC means 3, and if no error is detected, this bit sequence is output as decoded data and the decoding operation is terminated, and if any error is detected, the decoding operation is terminated an error detection.
FIG. 32 is a block diagram showing configuration of an error correcting/decoding apparatus for correcting errors in concatenated code based on the conventional technology shown in Japanese Patent Laid Open Publication No. HEI 6-284018. In this figure, designated at the reference numeral 1 is a demodulator, at 3 a CRC means, at 13 a multi-traceback Viterbi decoder capable of selecting a subset of candidates, when executing Viterbi decoding according to the soft-decision estimate output from the demodulator 1, by executing traceback several times, at 6 a bit sequence storing means for storing therein a bit sequence output from the CRC means, and at 14 a decoded data selector for selecting one candidate from the subset of candidates.
Next description is made for operation. At first, demodulation is executed in the demodulator 1, and at the same time soft-decision estimate for a received signal is computed from amplitude and a phase of a received signal. In the multi-traceback Viterbi decoder 13, a subset of paths are stored when ACS (Add Compare Select) is executed according to the soft-decision estimate generated in the demodulator 1, and when decoded data is obtained by means of traceback, a subset of bit sequences are obtained by executing traceback for each of the paths in the subset. Error detection is executed by the CRC means 3 to the subset of bit sequences obtained as described above, and a candidate in which no error is detected is stored in the bit sequence storing means 6, and final decoded data are decided by a decoded data selector 14 from the candidates, then the decoding operation is terminated.
However, in the concatenated code error correcting/decoding apparatus based on the conventional technology shown in FIG. 31, if an error is present even in one bit when Viterbi decoding is executed, an error is detected by CRC, so that the number of detected errors increases, and resultantly the effect provided by the error correcting capability becomes disadvantageously lower.
Also in the concatenated code error correcting/decoding apparatus based on the conventional technology shown in FIG. 32, traceback is executed several times, and a promising candidate is selected from a subset of candidates obtained through the traceback operation above to be treated as decoded data, and thus it becomes possible to perform an error correcting/decoding operation with higher reliability leaving paths aborted in the error correcting/decoding apparatus based on the conventional technology shown in FIG. 31, but as traceback is executed several times leaving a subset of candidates when ACS is executed, a work load for computing substantially increases, which is disadvantageous.